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[cvs-checkins] dbg_interface/rtl/verilog dbg_registers.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] dbg_interface/rtl/verilog dbg_registers.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] dbg_interface/rtl/verilog dbg_defines.v dbg_re ...
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[cvs-checkins] wb2hpi/apps/pci2dsp/syn/synplify/src regPCI.sdc
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[cvs-checkins] pci/apps/test/syn/synplify pci_test_top.prj
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[cvs-checkins] pci/ ench/verilog/pci_regression_constants.v e ...
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[cvs-checkins] mem_if/bench/verilog wb_bus_mon.v
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[cvs-checkins] mem_if/bench/verilog mem_if_bench.v wb_bus_mon.v
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[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v tl/verilog ...
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[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...
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[cvs-checkins] camera/rtl/verilog camera_cb_table.v camera_cr ...
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[cvs-checkins] Aquarius/doc Aquarius.pdf
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[cvs-checkins] Aquarius/doc Aquarius.doc
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[cvs-checkins] Import
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[cvs-checkins] ethernet/sim/rtl_sim/bin ncelab.args ncelab_xi ...
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[cvs-checkins] ethernet/sim/rtl_sim/run run_eth_sim_regr.scr
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_bsp.v
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[cvs-checkins] ethernet/sim/rtl_sim/log dir_keeper
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[cvs-checkins] ethernet/sim/rtl_sim/log
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[cvs-checkins] ethernet/sim/rtl_sim/run clean run_eth_sim_reg ...
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[cvs-checkins] ethernet/sim/rtl_sim/run
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[cvs-checkins] ethernet/sim/rtl_sim/out dir_keeper
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[cvs-checkins] ethernet/sim/rtl_sim/out
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[cvs-checkins] ethernet/sim/rtl_sim/bin artisan_file_list.lst ...
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[cvs-checkins] ethernet/sim/rtl_sim/bin/INCA_libs/worklib
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[cvs-checkins] ethernet/sim/rtl_sim/bin
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[cvs-checkins] ethernet/sim/rtl_sim/bin/INCA_libs
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[cvs-checkins] ethernet/sim/rtl_sim/ncsim_sim/run run_eth_sim ...
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[cvs-checkins] pyramid_unit/. Integer multiplication algorith ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_registers.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_top.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_bsp.v
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[cvs-checkins] can/rtl/verilog can_fifo.v
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[cvs-checkins] can/rtl/verilog can_acf.v
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[cvs-checkins] can/rtl/verilog can_btl.v
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[cvs-checkins] can/rtl/verilog can_crc.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_bsp.v
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[cvs-checkins] camera/bench/verilog camera_bench_top.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] camera/rtl/verilog camera_wb_if.v camera_top.v
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[cvs-checkins] camera/rtl/verilog camera_wb_if.v camera_top.v
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[cvs-checkins] camera/rtl/verilog async_reset_flop.v camera_d ...
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[cvs-checkins] camera/rtl/verilog async_reset_flop.v camera_d ...
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[cvs-checkins] oc8051/bench/verilog oc8051_serial.v
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[cvs-checkins] camera/rtl/verilog async_reset_flop.v camera_c ...
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[cvs-checkins] camera/rtl/verilog camera_y_table.v camera_tpr ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] hierarch_unit/. hierarchical_unit.tar.gz
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[cvs-checkins] hierarch_unit
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[cvs-checkins] common/. opencores_coding_guidelines.doc openc ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] Aquarius/doc Aquarius.doc Aquarius.pdf
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] Aquarius/doc Aquarius.doc Aquarius.pdf
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] Import
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] uart16550/rtl/verilog uart_rfifo.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] or1k/xess/xsv_fpga/orp_soc/rtl/verilog tc_top.v
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[cvs-checkins] or1k/orp/orp_soc/rtl/verilog/or1200 Tag: branc ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_top.v can_btl.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] pyramid_unit/. pyramid_unit.tar.gz
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] pyramid_unit
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] camera/rtl/verilog camera_cb_table.v camera_cr ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_bsp.v can_btl.v can_regist ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] or1k/or1ksim/mmu immu.c
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[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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[cvs-checkins] ethernet/rtl/verilog xilinx_dist_ram_16x32.v
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[cvs-checkins] or1k/gcc-3.2.3/gcc/fixinc gnu-regex.c
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[cvs-checkins] or1k/orp/orp_soc/sw/icm
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[cvs-checkins] or1k/orp/orp_soc/sw/icm Tag: branch_qmem Makef ...
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[cvs-checkins] or1k/orp/orp_soc/rtl/verilog/or1200 Tag: branc ...
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[cvs-checkins] or1k/orp/orp_soc/rtl/verilog/or1200 Tag: branc ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] spi/rtl/verilog spi_shift.v spi_top.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] spi/rtl/verilog spi_shift.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_top.v can_registers.v can_ ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] CVSROOT/rel1.0
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] camera/bench/verilog camera_bench_top.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] camera/sim core_sw_simulator/yuv422_to_rgb cor ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] spi/rtl/verilog spi_defines.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] spi/rtl/verilog spi_defines.v spi_shift.v spi_ ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] Import
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] spi/rtl/verilog spi_clgen.v spi_defines.v spi_ ...
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[cvs-checkins] i2c/doc i2c_specs.pdf src/I2C_specs.doc
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_top.v can_btl.v can_bsp.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] can/rtl/verilog can_fifo.v
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] oc8051/rtl/verilog oc8051_memory_interface.v o ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] oc8051/rtl/verilog oc8051_acc.v oc8051_alu.v o ...
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: OpenCores CVS Agent <cvs@www.opencores.org>
[cvs-checkins] or1k/or1ksim/cpu/or32 insnset.c
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[cvs-checkins] or1k/or1ksim/cpu or1k/opcode/or32.h or32/execg ...
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[cvs-checkins] oc8051/rtl/verilog oc8051_alu.v
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[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...
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[cvs-checkins] ps2/ ench/verilog/ps2_sim_top.v tl/verilog/ps2 ...
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