[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...

CVSROOT:	/home/oc/cvs
Module name:	mem_if
Changes by:	mihad	03/07/01 14:56:24

Modified files:
	bench/verilog  : mem_if_bench.v mem_if_sdram_flash_sim_top.v 
	rtl/verilog    : mem_if_registered_feedback.v mem_if_ro_top.v 
	                 mem_if_sdram_flash_defines.v 

Log message:
	Added wishbone rev. B3 signals to memory slave interface.
	No functionality added.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml