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[cvs-checkins] spi/rtl/verilog spi_clgen.v spi_defines.v spi_ ...



CVSROOT:	/home/oc/cvs
Module name:	spi
Changes by:	simons	03/07/03 16:32:34

Modified files:
	rtl/verilog    : spi_clgen.v spi_defines.v spi_shift.v spi_top.v 

Log message:
	8-bit WB access enabled.

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