[cvs-checkins] pci/ ench/verilog/pci_regression_constants.v e ...

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	03/07/29 10:21:28

Modified files:
	bench/verilog  : pci_regression_constants.v 
	                 pci_testbench_defines.v system.v wb_master32.v 
	                 wb_slave_behavioral.v 
	rtl/verilog    : pci_pcir_fifo_control.v pci_pciw_fifo_control.v 
	                 pci_wbr_fifo_control.v pci_wbw_fifo_control.v 
	sim/rtl_sim/run: run_pci_sim_regr.scr 
Added files:
	sim/rtl_sim/log: parse_monitor_logs.scr 

Log message:
	Found and simulated the problem in the synchronization logic.
	Repaired the synchronization logic in the FIFOs.

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