[cvs-checkins] camera/rtl/verilog async_reset_flop.v camera_d ...

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	camera
Changes by:	tadejm	03/07/15 09:36:11

Modified files:
	rtl/verilog    : async_reset_flop.v camera_defines.v 
	                 camera_io_calc.v camera_tpram.v 
	                 camera_cb_table.v camera_fifo_ctrl.v 
	                 camera_sync_ctrl.v camera_wb_if.v 
	                 synchronizer_flop.v camera_cr_table.v 
	                 camera_fifo.v camera_top.v camera_y_table.v 

Log message:
	BIST added for FIFO BLOCK RAM. BLOCK ROM changed to case sentence. Hierarchy vhanged.

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