[cvs-checkins] ethernet/rtl/verilog xilinx_dist_ram_16x32.v

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	simons	03/07/09 13:53:43

Added files:
	rtl/verilog    : xilinx_dist_ram_16x32.v 

Log message:
	This file was not part of the RTL before, but it should be here.

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