Re: [oc] I2C: help with ack timing

[Richard Herveille <richard@asics.ws>]

>Richard,
>
>Yes, that is precisely the problem I am seeing.
>
>Is this problem documented on the web site
>somewhere?  It would have saved me some time
>if a known problem was listed there.

No it isn't, sorry about that. I was working on the bug, but I am really 
swamped with work.

>This is working for me now, but I am not terribly
>happy with it and would like to verify it more
>before submitting it as a solution.
>
>As I mentioned, I am not using the wishbone
>interface so I don't know if this would be the
>proper fix for that situation.

As far as the main-engine is concerned there is no difference between the 
simple_i2c and the wishbone version. The wishbone version has some 
enhancements, some of which are a first step to support true multi 
master/slave operation.

I haven't examined the bug as in depth as you have. I wanted to try to 
change the cmd_ack timing to fix it (either the cmd-ack from the 
bit_controller or/and the cmd-ack from the byte_controller).

But if you feel this does not work and your solution is the correct one and 
it works, let's use it.

Richard


>Does this solution sound reasonable or did you
>have something else in mind?
>
>Tom
>Richard Herveille wrote:
> >
> > Ok everyone,
> >
> > Here's the problem. There's a problem with the I2C core concerning read-ack
> > timing. The interrupt signal and the TIP signal are asserted resp. negated
> > to early (before the ACK bit has been read). This is a known bug caused by
> > the cmd-ack (command acknowledge) signal being generated to early. But I
> > don't have the time at the moment to fix it. Please be patient (or try to
> > fix it yourself and send the fix back to CVS or me).
> >
> > Richard
> >
>
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