Re: [oc] Silicon Implementation

[John Sheahan <jrsheahan@optushome.com.au>]

On Tue, Mar 12, 2002 at 04:53:03PM -0800, Ali Mashtizadeh wrote:
> John Sheahan wrote:
> > 
> > On Tue, Mar 12, 2002 at 07:48:54AM -0800, Ali Mashtizadeh wrote:
> > 
> > I forgot to mention the scan , membist and jtag tools tools needed
> > for the asic too.
> > >
> > > Can you suggest a FAST FPGA that uses Antifuse or NVRAM? 300K to 500K.
> > > Cheap and low power? Price is more important than power I will probably
> > > have to use a Li-ion battery anyways.
> > 
> > Can you give me a hint as to what 'fast' is here and how many registers may
> > clock at that rate?  approx how many IO, what flavor, what speed.
> about 150 IO pins, and I would like to operate my design at 200-300Mhz.
> I've synthesized my parts and the largest delay seems too limit the
> design to a little 100Mhz on a Spartan II 200K.

placemet matters.  In an asic, placement is nearly the only thing that
matters.    I'd need to review your design for routability to comment. 
Whats the average fanout out of interest?
 


> > 
> > 400k asic gates would be 20Kff's, but if you are using
> > fgpa accounting could be less.

> I'm using an estimate from Xilinx Spartan II since I havn't synthesized
> the whole thing and my estimate based on how much the parts take
> seperately shows I need about 300K - 500K gates. (I have two projects).

again - are these asic gates of fpga gates. 
whats the max logic depth between flops? how many flops?

> 
> > Actel have biggish antifuse stuff.
> Yes, actel's the best I've found so far, I'll have too wait until they
> reach their goal in a couple of months for the lower end ProAsic+ since
> the price of those are a lot better than what I've seen for quicklogic
> and it's fast with pleanty of block ram for cache and tlb etc. I was
> looking for 10KBs or so and their close and even more than enough if I
> get the APA450. Do you have any experience with actel chips that you
> could compare the performance/density between actel proasic and some
> xilinx chip (Spartan II or Virtex).
> 

I used to represent actel many years ago.  Place and route it and do STA
before being convinced.   Are the programmers any cheaper than they
used to be?   They work when STA passed though. 
Rhere used to be a an issue over the current density required to blow
the antifuse making it hard to shrink metal pitch. Don't
know how that got resolved.  

> > Cypress has ee stuff that large.
> I'll check them out.
> > quiklogic has/had some interesting stuff too.
> Quicklogic's too expensive, Prices are a lot steeper than xilinx.
> 

yes. and sometimes faster.

> > 
> > the sram based things (eg virtex or spartan out of Xilinx, apex and
> > acex out of Altera is a two chip solution, not one,  but usually is
> > lower power.    I [refer these architectures.
> > some of them now have encrypted bitmaps for security if thats the
> No, I just want instant on feature and don't you have to keep the FPGA
> with a battery to power the decryption key?

instant on just means keeping a sram based device configured and not 
clocking.  Yes, the enryption did seem to require voltage which is an
issue.  But not if you own the code and the battery.

and if your simulation has issues (mine often do first time as I
understand and rewrite the spec) sram or ee wins out over antifuse.
Consider proto'ing in sram anyway, perhaps moving to antifuse later.
 
Also doing reprogrammable logic in sram stuff can be real fun. 
Thats where it shines. hard to design though.

> 
> > issue.  Soldering down those ball grids will be a pain.
> Ball grids aren't that bad. Just heat them up from under the board and
> they just sink in, it's a pain getting it in the right position though.

better you than me :) 
john


> 
> > 
> > I'm sure there are a bunch more I've not looked at or forgotten..
> > 
> > john
> > 
> > --
> > To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
> --
> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml