[oc] FREE simulation models and synthesis models for RAM and ROM

[Frederic RENOUX <ragtime@dolphin.fr>]

Title: FREE simulation models and synthesis models for RAM and ROM

Hello,

We are a Silicon IP provider and among the products we design are embedded memories. To simplify design-in, memory evaluation... we now propose FREE and on-line generation of Front-End views for RAM and ROM in various processes.

Front-end views which can be generated (VHDL or Verilog-HDL simulation model, Synopsys model...) can be used by designers to start their SoC/ASIC designs without requiring to enter in any heavy process (NDA...).

Direct link to the appropriated page on our web site:
<http://www.dolphin.fr/flip/ragtime/025/ragtime_025_download.html>

We think that this could be an interesting opportunity for your readers to get access these FREE solutions and would be please to cooperate with you to inform them about this capability and to post a link on your web site.

Please let me know about your interest.

Best regards,

Frederic Renoux
FLIP Marketing and Sales

-- 
DOLPHIN Integration
"The Enabler of mixed signal Systems-on-Chip"
F-38242 Meylan FRANCE
direct phone: 33 (0) 476 41 74 09
fax:          33 (0) 476 90 29 65
http://www.dolphin-ip.com
 mailto: ragtime@dolphin.fr