Re: [oc] TLB Design

["Jim Dempsey" <tapedisk@ameritech.net>]

----- Original Message ----- 
From: "Ali Mashtizadeh" <ali@alikat.org>
To: <cores@opencores.org>
Sent: Tuesday, February 26, 2002 8:00 PM
Subject: [oc] TLB Design


> Well I understand that I am supposed to use a state machine to do the
> comparisons. It's like this
> 
> virtual Address->[Content Addressable Memory(State
> machine)]->[RAM]->Physical Address
> 
> The CAM(Content Addressable Memory) is my problem. You need to use a
> state machine to do the comparisons but that means if you have a 64
> entry tlb then it will take 64 clock cycles. Unless you make the state
> machine's clock to be 64 times faster.

The time to check n cells of a CAM is the same as the time to check 1 cell.
That is what CAM is all about. 

> I understand that most cpu's
> break up the process into several smaller blocks of 4 or 8 entries and a
> seperate comparator for each block but still that means I have to use up
> my precious DLL's. 

cost/performance issue

> As for a TLB compatible with a 386 your gonna have
> fun with that. You need to make a search state machine to find entries
> out of the page tables when it is not in the TLB cache.
> 

Or it is part of your microcode. A miss on the CAM requires a function call
(in the microcode).


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml