Re: [oc] CRC calculation.

[Allan Herriman <allan_herriman.hates.spam@agilent.com>]

Hi Blue,

llbutcher wrote:
> 
> Naveena:
> 
> I made a CRC checker which I stored in misc/crc32_lib.v
> There is nothing original in there.  I mostly tried to see if
> there was a way to break up the calculation so that it had
> a minimum number of logic levels.
> 
> I wonder how fast you need to calculate your CRC.
> 
> If you have a slow serial link, a bit-at-a-time calculation seems best.
> 
> If you need a faster one, I suggest a wide calculation followed by
> transfering the partial CRC to a smaller CRC function, where you
> calculate the effect of the bytes which don't fill up the larget block.
> 
> I think that a 64 bit version, or at worst a 128 bit version, should
> be able to keep up with a 10 GBit connection in a fast FPGA.

You reach a point where making the bus wider doesn't make the CRC
faster, in terms of bits per second.  The number of inputs to each XOR
grows with the bus width.

I was doing some parallel PRBS experiments recently, and I found in some
cases that the 128 bit bus produced lower bit rates than a 64 bit
design.


64 bits is adequate for a CRC at 10 Gbit/s in an FPGA, BTW.


Has anyone worked out what the OP is trying to do yet?

Allan.

> hi Allan,
> 
> In our logic, input data to hdlc is variable. My internal input buffer is
> 128bit,bcose for 128bit processing.output of this is i am send it to CRC
> calculator. so i want to do crc calculation for 128bit data, this data is
> again variable from 1byte to 16byte.how can i do the crc for this.
> 
> Thanks & Rgds...
> 
> -Naveena P.
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml