Re: [ethmac] Ethernet core on FPGA - WISHBONELESS INTERFACE!

[nubiron@hotmail.com]

----- Original Message ----- 
From: simos@c...  
To: ethmac@o...  
Date: Thu, 1 Aug 2002 14:53:39 -0100 
Subject: [ethmac] Ethernet core on FPGA - WISHBONELESS INTERFACE! 

> 
> 
> Hello everybody and congratulations on the feedback sofar! 
> 
> I want to write an Ethernet core to be used in future designs, but 
> without having to use wishbone interface on the host interface part 
> of 
> the design. 
> 
> As I can see, the ethernet core communicates with the host only by 
> using DMA transfers. Additionally, wishbone interface has to be 
> used 
> throughout the design. 
> 
> Has anybody used the ethernet core on an FPGA but with another 
host 
> interface (lets say a small memory and a loopback part)? 
> 
> I am using MaxPlus and Quartus and implement the designs on a 
> FLEX10K100 FPGA. 
> 
> Thanx in advance! Looking forward 2 hearing from u ASAP! 
> 
> Mimis Simos. 
> 

Hey man!I got the answer right here!This person I know i really 
something when it comes to anything that has to do with computers.
There is one big but...
You have to beat him on a game of pool,ya know what I'm saying?
Do that and all your problems will be solved.

Cheers mate!Say hello to Andrianna from me!Hehehe... ;-)
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