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[oc] Re: Sequential processing in VHDL? Whats the best way to do it?
On Fri, Dec 07, 2001 at 12:23:27PM -0000, Paul McFeeters wrote:
> Hi,
>
> I have started working on my own version of Handel-C to convert C into VHDL
> (couldn't find $75,000 laying around the house). The first problem I
> obviously encountered was that VHDLs sequential processes don't work as
> high-level programmers would expect them to. I'm using signals for global
> variables but in VHDL sequential logic processes the signals are not
> actually updated until the process finishes. Hence as we all know the
> following example IF statement always fails.
>
> -- on entry x is always 10
> check_x : process (clock)
> begin
> x <= 6 ;
> if (x = 6) then
> -- this code section will never be called as x will only change after the
> process has finished
> end if ;
> end process ;
Actually the if block will be run, but on the next transition of clock
when x will be 6. Use variables instead of signals to do sequential
calculations and assign the final result to a signal.
If you want to synthesize that code into real hardware it depends on the
cleverness of the synthesizer whether it can do that or simply choke on
it.
--
Andreas Bombe <bombe@informatik.tu-muenchen.de> DSA key 0x04880A44
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