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[cvs-checkins] can/rtl/verilog can_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] can/rtl/verilog can_top.v
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Tue, 17 Jun 2003 13:30:54 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/06/17 13:30:54

Modified files:
	rtl/verilog    : can_top.v 

Log message:
	"chip select" signal cs_can_i is used only when not using WISHBONE
	interface.

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