[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] oc8051/rtl/verilog oc8051_defines.v oc8051_ram ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] oc8051/rtl/verilog oc8051_defines.v oc8051_ram ...
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Tue, 17 Jun 2003 13:17:39 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	oc8051
Changes by:	simont	03/06/17 13:17:39

Modified files:
	rtl/verilog    : oc8051_defines.v oc8051_ram_top.v oc8051_top.v 

Log message:
	BIST signals added.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] can/rtl/verilog can_bsp.v
Next by Date: [cvs-checkins] can/rtl/verilog can_bsp.v
Prev by thread: [cvs-checkins] can/rtl/verilog can_top.v
Next by thread: [cvs-checkins] can/rtl/verilog can_bsp.v
Index(es):
- Date
- Thread