[oc] Synplicity

["naveen jain" <navjain@hotmail.com>]

Hi,
      Does anybody had problem with synplicity 6.2 when it is inferring RAM, 
as it is messing up in vhdl output for simulation.
Quartus output is fine. Secondly if you have state machine in
procedure, it doesn't make logic correctly. Does anybody
faced any problem like this, if yes, how you resolved it.
Thanks
Nav

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