Re: [oc] SHA-1

[Dian Tresna Nugraha <diantn@yahoo.com>]

Dear Aria,

Basically, you always be able to read/write file with VHDL. 
For example, using these processes to read from stimuli file and to
write the output response, inside a testbench architecture.

-- W_VALUE_1 and W_VALUE_2 are signals inside architecture.
STIMULI : process
  variable L_IN : line;
  variable CHAR : character;
  variable DATA_1 : std_logic_vector(7 downto 0);
  variable DATA_2 : std_logic_vector(7 downto 0);
  file STIM_IN : text is in "stim_in.txt";
begin
  W_VALUE_1 <= (others => '0');
  W_VALUE_2 <= (others => '0');
  wait for PERIOD;
  while not endfile (STIM_IN) loop
    readline (STIM_IN, L_IN); -- read one line
    read (L_IN, DATA_1); -- read 8 bit into DATA_1
    W_VALUE_1 <= DATA_1; -- assign into W_VALUE_1 signal
    read (L_IN, CHAR); -- read the space
    hread (L_IN, DATA_2); -- read 8 bit hexadecimal to DATA_2
    W_VALUE_2 <= DATA_2; -- assign into W_VALUE_2 signal
    wait for PERIOD;
  end loop;
  wait;
end process STIMULI;

-- W_RESULT is signal inside architecture.
RESPONSE : process(W_RESULT)
  variable L_OUT : line;
  variable CHAR_SPACE : character := ' ';
  file STIM_OUT : text is out "stim_out.txt";
begin
  write (L_OUT, now);
  write (L_OUT, CHAR_SPACE);
  write (L_OUT, W_RESULT); -- write line buffer the binary/9 value
logic form of W_RESULT
  write (L_OUT, CHAR_SPACE);
  hwrite(L_OUT, W_RESULT); -- write line buffer in hexadecimal form
  writeline (STIM_OUT, L_OUT); -- write the line buffer to file
end process RESPONSE

The input file "stim_in.txt" has this data format:
00000000 A1
11111111 01
11111111 00
00010001 55
00001111 01
00011111 05
11001100 F3

Also make sure that you use the following library 
library IEEE;
use IEEE.std_logic_textio.all;
use STD.textio.all;

which can be put before the entity description of the testbench.

Regards,



Dian.


--- I Made Aria Bagus P <aria@students.ee.itb.ac.id> wrote:
> 
> Dear all,
> 
> I have so far completed designing a hardware of SHA-1 in the form
> of VHDL
> and at this moment, i need to verify it and that will require a
> VHDL
> program that can read and write files. is there a free core about
> it?
> 
> regards,
> 



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