[oc] OCIDEC core revisions

[Richard Herveille <richard@asics.ws>]

Hi everybody,

I've made some major changes to the OCIDEC cores.
The changes are to many to enter them all here.
To name a few:

- synthesis related changes. I made a number of changes to my internal 
counter libraries, because there are reports that it was difficult to 
insert a scan-chain into the cores. (Hopefully this fixes it)
- I changed the IO names to reflect the new guidelines.
- I added a Verilog version of the OCIDEC-2
- I made a number of structural changes to make it easier to port and 
maintain the cores. It should be very straightforward to port the OCIDEC-3 
core to Verilog now.
- etc.
- I updated the documentation to reflect all these changes. The 
documentation however is still very preliminary.

Richard

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