RE: [oc] ALDEC Vs. ModelSIM (VHDL Simulator)

["Morris, Scott J" <morris.scott@pnl.gov>]

I have the ALDEC VHDL simulator, but have never used the MODELSIM sim.  For
my purposes the ALDEC sim is great.  They provide a signal stimulator that I
can easily put my signals into the proper place and test out simple designs.
I havn't played much with their testbench maker so can't comment on that.  I
havn't used on many large designs but the few I have I found that it was
reasonably fast.

Scott

> -----Original Message-----
> From: ramkripalec@yahoo.co.uk [mailto:ramkripalec@yahoo.co.uk]
> Sent: Friday, February 08, 2002 3:19 AM
> To: cores@opencores.org
> Subject: Re: [oc] ALDEC Vs. ModelSIM (VHDL Simulator)
> 
> 
> 
> 
> ----- Original Message ----- 
> From: Jimmy Hui <Jimmy_Hui@a... > 
> To: "'cores@o... '" <cores@o... > 
> Date: Tue, 4 Apr 2000 10:33:11 -0700 
> Subject: [oc] ALDEC Vs. ModelSIM (VHDL Simulator) 
> 
> > 
> > 
> > Has anyone used the ALDEC  VHDL simulator (current version is 3.6, 
> > www.aldec.com free eval)?  How is it compared to the one by 
> > MODELSIM (Model 
> > Technology)? 
> > 
> > Thanks, 
> > 
> > Jimmy 
> > 
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