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[oc] Query abt Switch level modelling in Verilog



Hi All,
 
Can any one kindly answer my query? I want to know if the MOS switches and other lowest-level primitives that verilog supports are used by any one, either in their simulation environment or in their RTL code. If YES, then where exactly are they being used? 
 
Thanks in Advance!


R Ramakrishna

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