Re: [oc] Re: How to create such signal wave using VHDL?

["Marko Mlinar" <markom@opencores.org>]

> for my 2pence worth, I know people have done a combined Ethernet and
TCP/IP stack in a
> single FPGA which I think is pretty cool. Although they did 'cheat' and
used a C to netlist
> compiler instead of Verilog but if you are up for a challenge I think its
a neat idea. Given
> the popularity of TCP/IP these days it would give you a nice boost when
they ask you at
> interviews "do you have any experience of TCP/IP?".
How much time you think one person would need to finish such project?

Marko


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