RE: [oc] Re: How to create such signal wave using VHDL?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Ramakrishna,

for my 2pence worth, I know people have done a combined Ethernet and TCP/IP stack in a
single FPGA which I think is pretty cool. Although they did 'cheat' and used a C to netlist
compiler instead of Verilog but if you are up for a challenge I think its a neat idea. Given
the popularity of TCP/IP these days it would give you a nice boost when they ask you at 
interviews "do you have any experience of TCP/IP?".

Paul



> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Ramakrishna Rayaprolu
> Sent: 20 December 2001 11:53
> To: cores@opencores.org
> Subject: RE: [oc] Re: How to create such signal wave using VHDL?
> 
> 
> hi all!!
> i have been observing the interesting conversations
> going on thru these mails. and i feel happy tht i am a
> part of it.
> 
> i am a fresher from OU, Hyderabad, India. i have a
> background in verilog coding of a few simple cores
> like a fifo controller, implementation of booths alg,
> a simple microcontroller(reasonably simplified, o'coz)
> now that i'm in my final sem, i am required to
> complete a decent project. can any one help me with an
> interesting core to code in verilog? i am inclined to
> code some networking protocol which might give my
> career a good start. but i am ready to take up any
> thing which is good enough to stand as a graduate
> project. 
> 
> i request all of u to help me out.
> 
> Thank you.
> 
> Ramakrishna
> 
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