Re: [oc] VHDL help.

["Andras Tantos" <andras_tantos@yahoo.com>]

Hi!

> Hello,   Can anyone please tell me in detail ( & in simple terms ) what
exactly the
> following VHDL functions do ?Also, are they supported for synthesis,
especially in
> Xilinx Foundation-F3.1i tool ?Thanks in advance.   Kausar.  [
kausarahmedr@yahoo.com ]
> [1] FUNCTION to_high_imped(arg : bvec) RETURN bvec IS
>           VARIABLE result : bvec;
>       BEGIN
>            FOR k in arg'RANGE LOOP
>              CASE arg(k) IS
>                   WHEN '0' => result(k) := 'L';
>                   WHEN '1' => result(k) := 'H';
>                   WHEN 'L' => result(k) := 'L';
>                   WHEN 'H' => result(k) := 'H';
>                   WHEN OTHERS => result(k) := 'Z';
>              END CASE;
>           END LOOP;
>         RETURN(result);
>      END FUNCTION to_high_imped;
>---------------------------------------------------------------

I might be wrong but it seems that it converts high-force values ('0' and
'1') to low-force ones ('H' and 'L') in a bit-vector. That comes handy for
multiple-source-driven signals with standard resolution-functions. When a
wire is driven to 'L' another driver can drive it to '1' and similary if a
driver drives the wire to 'H' another one can drive it to '0'. Driving a
signal to '1' on ne hand and to '0' on the other is an error. Driving it to
both 'L' and 'H' results in a 'weak unknown' 'W'. 'Z' has the lowest
enforcement. It can be overwritten by both 'L' 'H' '1' and '0'. All
description above are for STD_LOGIC signals with the standard resolution
function.

Multiple-source-driven signals are supported by Xilinx Foundation as far as
I know, only a warning is issued during compilation. So my guess is that
this fuction should work with that tool.

Hope it helps,
Andras Tantos

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