Re: [oc] UART16550 core

[Richard Herveille <richard@asics.ws>]

Hey guys,

Stop talking this crap. CYC_O/CYC_I are probably the most important signals 
on the bus. The CYC signal qualifies all other signals. Each slave MUST 
evaluate this signal. When it is negated all other signals MUST be ignored, 
because they are not valid.

 From a hardware point of view, this means a slave should respond when 
CYC_I and STB_I are both asserted:
    i_am_addressed <= CYC_I & STB_I;

Concerning the wishbone_burst discussion. These issues will be resolved in 
the revision C of the wishbone specs. For now it is enough to say that 
burst-transfers are fully supported and that the wishbone specs will be 
extended for this purpose.
Please use the revision B2 specs for now. This is still a working document, 
but much better than the rev.B specs.

Richard

>Hi Carl,
>
> > I'm not too sure what you mean?
> > CYC_O from the master is not a very important signal, a slave can
> > ignore it if it wants. All I did was use it to qualify the Read/Write
> > enable signals . The wishbone speci is very vague when it
> > comes to the slaves handling of this signal.
>
>CYC_I/CYC_O signals are very important when it comes to bus arbitation. You
>are right in one thing: most slave devices don't need them. However bus
>arbiter 'slaves' do make use of those signals and also can slaves if they
>support 'bursts'. (BTW what is the status on the discussion about bursts on
>the Wishbone bus?)
>
>regards,
>Andras
>
>
>
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