Re: [oc] UART16550 core

["Andras Tantos" <andras_tantos@yahoo.com>]

Hi Carl,

> I'm not too sure what you mean?
> CYC_O from the master is not a very important signal, a slave can
> ignore it if it wants. All I did was use it to qualify the Read/Write
> enable signals . The wishbone speci is very vague when it
> comes to the slaves handling of this signal.

CYC_I/CYC_O signals are very important when it comes to bus arbitation. You
are right in one thing: most slave devices don't need them. However bus
arbiter 'slaves' do make use of those signals and also can slaves if they
support 'bursts'. (BTW what is the status on the discussion about bursts on
the Wishbone bus?)

regards,
Andras



_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml