[oc] ACEX 1K50 on JTAG

[Daniel Haensse <daniel.haensse@alumni.ethz.ch>]

Hi folks,

I'm working on a openhardware project using the 68vz328 and a Altera fpga.
I would like to download the code to the fpga using the jtag interface.
I have found the jbc player that is easy to port to different platforms, but 
it need the jbc format from the compiler. I can't find any switch
to tell the compiler to generate jbc code within the altera basline software.
Does anybody know how to generate jbc code on this acex 1k50
chips?

Thanks Dani
To unsubscribe from a cores mailing list please visit
http://www.opencores.org/mailinglists.shtml