Re: [oc] SoC bus review

[John Dalton <johnd@southern-poro.com>]

Damjan Lampret wrote:
>  How about scan chain for ASIC verification.

Possibly.  I'm not sure a scan chain belongs in a "SoC
bus" specification in the usual sense of the word.  Could
putting JTAG into a SoC bus spec limit choice of testing
methodology?  What happens if someone uses (or invents)
a non-JTAG based test method?

How about another level of specification above
the "SoC bus", which includes an "SoC bus" and a test
interface? (Use a fixed width font to see the ASCII art.)

  LEVEL x                 LEVEL x+1

SoC interface  ---|--- SoC uP type bus (wishbone, AMBA, CoreConnect, etc.)
                  |
                  |--- Test bus (JTAG, etc.)

And taking a slightly wider view

  LEVEL x-1                      LEVEL x

 FPGA Module Standard  ---|--- SoC interface (as above)
                          |
                          |--- Power Supply Bus