Re: [oc] Wishbus Bus

[Rudolf Usselmann <rudi@asics.ws>]

Winefred

You are right, wishbone does not support dynamic bus sizing. Which is
actually good, as it simplifies the overall design.
Of course there will be areas, such as you pointed out, where dynamic
bus sizing would be nice to have. However, those are rather rare, and
for an SoC bus less imported then simplicity.
If you are building a PCI<->Wishbone bridge (which would be super, super
cool :*) you will need additional information (such as bus width) from
the devices that you are talking to. This should be easy and straight
forward to add ....

Best Regards,
rudi



on 12/31/00 11:14, Winefred Washington at wwashington@austin.rr.com wrote:
> We may need to make an additional requirement to the Wishbone spec or
> perhaps Silicore is already working on it.
> 
> I was working on a simple testbench and here's the problem I think I found.
> A master device has to know what the bus width of the slave device is for
> the transfer to work correctly. Suppose we have a 32-bit PCI to Wishbone
> device and it has to transfer data to 32-bit  and an 8-bit devices. The PCI
> core has to change how the data is presented on the bus to match the data
> width of the slave devices. That means the PCI core has to contain logic
> specific to the application which hurts reuse.
> 
> One solution is to fix the data widths to 32-bits for all cores.
> 
> Any comments?
> 
> Did I miss something in the spec?
> 
> WW
> 
> 
> 
>