lcdc_configuration_s Struct Reference

#include <lcdc.h>


Detailed Description

Struct that defines the configuration of the LCD controller.

Definition at line 58 of file lcdc.h.


Data Fields

unsigned char burst_length
 Burst length of DMA controller.
unsigned char clkmod
 Pixel clock mode.
unsigned char ctrst_ena
 Contrast PWM generator enable.
unsigned char ctrst_pol
 Contrast PWM polarity This value defines the polarity of the contrast PWM output. If NORMAL, the output pulses are high level (the output will be high whenever the value in the counter is less than the value in the compare register CONTRAST_VAL ctrstval ). If INVERTED, the output pulses are low level.
unsigned char ctrst_ps
 Contrast PWM prescaler This Prescaler divides the LCD controller clock for the contrast PWM generator.
unsigned char ctrstval
 Contrast value PWM compare value used to adjust the analog value obtained after an external filter to control the contrast of the display.
unsigned char distype
 Display type.
unsigned int dmabaddr1
 Base address for the upper panel (in dual scan mode) or complete frame.
unsigned int dmabaddr2
 Base address of lower panel (dual scan mode only.
unsigned short frame_rate
 Frame rate of the display.
unsigned short guard_time
 Delay in frame periods between applying control signals to the LCD module and setting PWR high, and between setting PWR low and removing control signals from LCD module.
unsigned char hbp
 Horizontal back porch Number of idle pixel clock cycles at the beginning of the line. Idle period is (HBP+1) pixel clock cycles.
unsigned char hfp
 Horizontal front porch Number of idle pixel clock cycles at the end of the line. Idle period is (HFP+1) pixel clock cycles.
unsigned short hpw
 Horizontal sync pulse width Width of the HSYNC pulse, given in pixel clock cycles. Width is (HPW+1) PCLK cycles.
unsigned char ifwidth
 Interface width (only valid for STN mode).
unsigned char invclk
 Pixel clock polarity.
unsigned char invdval
 Data valid polarity.
unsigned char invframe
 Vertical sync polarity.
unsigned char invline
 Horizontal sync polarity.
unsigned char invvd
 Data polarity.
unsigned int lcdcclock
 LCD controller clock Frequency in MHz at which the LCD module runs. This can be set in the generic clock setup.
unsigned char memor
 Memory organization.
unsigned char mmode
 Toggle rate Toggle the polarity after each frame (EACH_FRAME) or by a specified value (MVAL_DEFINED).
unsigned char mval
 Toggle rate value. If Toggle rate is set to MVAL_DEFINED this value sets toggle rate to mval + 1 line periods.
unsigned char pixelsize
 Bits per pixel.
unsigned char scanmod
 Scan mode.
unsigned char set2dmode
 Enables or disables the 2D addressing mode If 2D addressing is activated the values in virtual_xres and virtual_yres must be set according to the virtual frame size.
unsigned char vbp
 Vertical back porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to 0.
unsigned char vfp
 Vertical front porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0.
unsigned char vhdly
 Vertical to horizontal delay In TFT mode, this is the delay between VSYNC rising or falling edge and HSYNC rising edge. Delay is (VHDLY+1) pixel clock cycles. In STN mode, these bits should be set to 0.
unsigned int virtual_xres
 Virtual horizontal size of the display (in pixels) Use this in 2D addressing mode to set the size of the frame buffer.
unsigned int virtual_yres
 Virtual vertical size of the display (in pixels) Use this value in 2D addressing mode to set the size of the frame buffer.
unsigned char vpw
 Vertical sync pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. VSYNC width is equal to (VPW+1) lines. In STN mode, these bits should be set to 0.
unsigned short xres
 Number of columns on the display (in pixels).
unsigned short yres
 Number of rows on the display (in pixels).

Field Documentation

Burst length of DMA controller.

Definition at line 64 of file lcdc.h.

Referenced by lcdc_init().

Pixel clock mode.

  • LCDC_PARTLY_ACTIVE (only active during display period)
  • LCDC_ALWAYS_ACTIVE (needed for TFT mode)

Definition at line 158 of file lcdc.h.

Referenced by lcdc_init().

Contrast PWM generator enable.

  • LCDC_ENABLED
  • LCDC_DISABLED

Definition at line 199 of file lcdc.h.

Referenced by lcdc_init().

Contrast PWM polarity This value defines the polarity of the contrast PWM output. If NORMAL, the output pulses are high level (the output will be high whenever the value in the counter is less than the value in the compare register CONTRAST_VAL ctrstval ). If INVERTED, the output pulses are low level.

  • LCDC_NORMAL
  • LCDC_INVERTED

Definition at line 193 of file lcdc.h.

Referenced by lcdc_init().

Contrast PWM prescaler This Prescaler divides the LCD controller clock for the contrast PWM generator.

  • LCDC_PRE_NONE No prescaling
  • LCDC_PRE_HALF LCD controller clock divided by 1/2
  • LCDC_PRE_FOURTH LCD controller clock divided by 1/4
  • LCDC_PRE_EIGTH LCD controller clock divided by 1/8

Definition at line 184 of file lcdc.h.

Referenced by lcdc_init().

Contrast value PWM compare value used to adjust the analog value obtained after an external filter to control the contrast of the display.

Definition at line 175 of file lcdc.h.

Referenced by lcdc_init().

Display type.

  • LCDC_STN_MONO
  • LCDC_STN_COLOR
  • LCDC_TFT

Definition at line 124 of file lcdc.h.

Referenced by lcdc_init().

Base address for the upper panel (in dual scan mode) or complete frame.

Definition at line 60 of file lcdc.h.

Referenced by increment_frame_base(), lcdc_init(), and main().

Base address of lower panel (dual scan mode only.

Definition at line 62 of file lcdc.h.

Referenced by lcdc_init().

Frame rate of the display.

Definition at line 89 of file lcdc.h.

Referenced by lcdc_init().

Delay in frame periods between applying control signals to the LCD module and setting PWR high, and between setting PWR low and removing control signals from LCD module.

Definition at line 98 of file lcdc.h.

Referenced by lcdc_init().

Horizontal back porch Number of idle pixel clock cycles at the beginning of the line. Idle period is (HBP+1) pixel clock cycles.

Definition at line 223 of file lcdc.h.

Referenced by lcdc_init().

Horizontal front porch Number of idle pixel clock cycles at the end of the line. Idle period is (HFP+1) pixel clock cycles.

Definition at line 228 of file lcdc.h.

Referenced by lcdc_init().

unsigned short lcdc_configuration_s::hpw

Horizontal sync pulse width Width of the HSYNC pulse, given in pixel clock cycles. Width is (HPW+1) PCLK cycles.

Definition at line 218 of file lcdc.h.

Referenced by lcdc_init().

Interface width (only valid for STN mode).

  • LCDC_IF_WIDTH4 (only valid in STN single scan mode)
  • LCDC_IF_WIDTH8
  • LCDC_IF_WIDTH16 (only valid in dual scan mode)

Definition at line 113 of file lcdc.h.

Referenced by lcdc_init().

Pixel clock polarity.

  • LCDC_NORMAL (data fetched at falling edge)
  • LCDC_INVERTED (data fetched at rising edge)

Definition at line 146 of file lcdc.h.

Referenced by lcdc_init().

Data valid polarity.

  • LCDC_NORMAL (active high)
  • LCDC_INVERTED (active low)

Definition at line 152 of file lcdc.h.

Referenced by lcdc_init().

Vertical sync polarity.

  • LCDC_NORMAL (active high)
  • LCDC_INVERTED (active low)

Definition at line 135 of file lcdc.h.

Referenced by lcdc_init().

Horizontal sync polarity.

  • LCDC_NORMAL (active high)
  • LCDC_INVERTED (active low)

Definition at line 141 of file lcdc.h.

Referenced by lcdc_init().

Data polarity.

  • LCDC_NORMAL
  • LCDC_INVERTED

Definition at line 129 of file lcdc.h.

Referenced by lcdc_init().

LCD controller clock Frequency in MHz at which the LCD module runs. This can be set in the generic clock setup.

Definition at line 95 of file lcdc.h.

Referenced by lcdc_init().

Memory organization.

  • LCDC_BIG_ENDIAN
  • LCDC_LITTLE_ENDIAN
  • LCDC_WIN_CE

Definition at line 106 of file lcdc.h.

Referenced by lcdc_init().

Toggle rate Toggle the polarity after each frame (EACH_FRAME) or by a specified value (MVAL_DEFINED).

  • LCDC_EACH_FRAME
  • LCDC_MVAL_DEFINED

Definition at line 206 of file lcdc.h.

Referenced by lcdc_init().

Toggle rate value. If Toggle rate is set to MVAL_DEFINED this value sets toggle rate to mval + 1 line periods.

  • LCDC_MVAL_DEFINED
  • LCDC_EACH_FRAME

Definition at line 213 of file lcdc.h.

Referenced by lcdc_init().

Bits per pixel.

  • LCDC_BPP_1
  • LCDC_BPP_2
  • LCDC_BPP_4
  • LCDC_BPP_8
  • LCDC_BPP_16
  • LCDC_24 (packed 24bpp)
  • LCDC_32 (unpacked 24bpp)

Definition at line 169 of file lcdc.h.

Referenced by increment_frame_base(), lcdc_init(), and main().

Scan mode.

  • LCDC_SINGLE_SCAN
  • LCDC_DUAL_SCAN

Definition at line 118 of file lcdc.h.

Referenced by lcdc_init().

Enables or disables the 2D addressing mode If 2D addressing is activated the values in virtual_xres and virtual_yres must be set according to the virtual frame size.

  • LCDC_MODE_2D_ON
  • LCDC_MODE_2D_OFF

Definition at line 76 of file lcdc.h.

Referenced by lcdc_init().

Vertical back porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to 0.

Definition at line 239 of file lcdc.h.

Referenced by lcdc_init().

Vertical front porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0.

Definition at line 244 of file lcdc.h.

Referenced by lcdc_init().

Vertical to horizontal delay In TFT mode, this is the delay between VSYNC rising or falling edge and HSYNC rising edge. Delay is (VHDLY+1) pixel clock cycles. In STN mode, these bits should be set to 0.

Definition at line 250 of file lcdc.h.

Referenced by lcdc_init().

Virtual horizontal size of the display (in pixels) Use this in 2D addressing mode to set the size of the frame buffer.

Definition at line 81 of file lcdc.h.

Referenced by increment_frame_base(), lcdc_init(), and main().

Virtual vertical size of the display (in pixels) Use this value in 2D addressing mode to set the size of the frame buffer.

Definition at line 86 of file lcdc.h.

Referenced by increment_frame_base(), and main().

Vertical sync pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. VSYNC width is equal to (VPW+1) lines. In STN mode, these bits should be set to 0.

Definition at line 234 of file lcdc.h.

Referenced by lcdc_init().

Number of columns on the display (in pixels).

Definition at line 66 of file lcdc.h.

Referenced by lcdc_init().

Number of rows on the display (in pixels).

Definition at line 68 of file lcdc.h.

Referenced by increment_frame_base(), and lcdc_init().


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