Definition in file sdramc_at32ap7000.h.
#include <avr32/io.h>
#include "MT481C2M32B2TG/mt481c2m32b2tg.h"
Go to the source code of this file.
Functions | |
void | sdramc_init (unsigned long hsb_hz) |
Initializes the AVR32 SDRAM Controller and the connected SDRAM(s). |
void sdramc_init | ( | unsigned long | hsb_hz | ) |
Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).
hsb_hz | HSB frequency in Hz (the HSB frequency is applied to the SDRAMC and to the SDRAM). |
Each access to the SDRAM address space validates the mode of the SDRAMC and generates an operation corresponding to this mode.
Definition at line 89 of file sdramc_at32ap7000.c.
References sdram_delay(), and sdramc_enable_muxed_pins().
Referenced by main().
00090 { 00091 00092 volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC; 00093 volatile U32 *sdram = (void *) BOARD_SDRAM_BASE; 00094 U32 i; 00095 00096 sdramc_enable_muxed_pins(); 00097 00098 // Setup SDRAM controller 00099 sdramc->cr = ( (SDRAM_COL_BITS - 8) << AVR32_SDRAMC_CR_NC ) | 00100 ( (SDRAM_ROW_BITS - 11) << AVR32_SDRAMC_CR_NR ) | 00101 ( (SDRAM_BANK_BITS - 1) << AVR32_SDRAMC_CR_NB ) | 00102 ( SDRAM_CAS << AVR32_SDRAMC_CR_CAS ) | 00103 ( SDRAM_TWR << AVR32_SDRAMC_CR_TWR ) | 00104 ( SDRAM_TRC << AVR32_SDRAMC_CR_TRC ) | 00105 ( SDRAM_TRP << AVR32_SDRAMC_CR_TRP ) | 00106 ( SDRAM_TRCD << AVR32_SDRAMC_CR_TRCD ) | 00107 ( SDRAM_TRAS << AVR32_SDRAMC_CR_TRAS ) | 00108 ( SDRAM_TXSR << AVR32_SDRAMC_CR_TXSR ); 00109 00110 sdram_delay(200); 00111 00112 // Precharge All command is issued to the SDRAM 00113 sdramc->mr = AVR32_SDRAMC_MR_MODE_BANKS_PRECHARGE; 00114 sdramc->mr; 00115 sdram[0] = 0; 00116 00117 // Provide eight auto-refresh (CBR) cycles 00118 sdramc->mr = AVR32_SDRAMC_MR_MODE_AUTO_REFRESH; 00119 sdramc->mr; 00120 for (i = 0; i < 8; i++) 00121 sdram[0] = 0; 00122 00123 // A mode register set (MRS) cycle is issued to program 00124 // SDRAM parameters, in particular CAS latency and burst 00125 // length. 00126 00127 // CAS from info struct, burst length 1, serial burst type 00128 sdramc->mr = AVR32_SDRAMC_MR_MODE_LOAD_MODE; 00129 sdramc->mr; 00130 sdram[0x020] = 0; 00131 00132 // A Normal Mode command is provided, 3 clocks after tMRD is met. 00133 sdramc->mr; 00134 sdramc->mr = AVR32_SDRAMC_MR_MODE_NORMAL; 00135 sdramc->mr; 00136 sdram[0] = 0; 00137 00138 // Write refresh rate into SDRAMC refresh timer count register 00139 sdramc->tr = ( ( 156 * (hsb_hz / 1000) ) / 10000 ); 00140 }