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00045 #include <avr32/io.h>
00046 #include "compiler.h"
00047 #include "tc.h"
00048
00049
00050 int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)
00051 {
00052
00053 if (channel >= TC_NUMBER_OF_CHANNELS)
00054 return TC_INVALID_ARGUMENT;
00055
00056 return tc->channel[channel].imr;
00057 }
00058
00059
00060 int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
00061 {
00062 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00063
00064
00065 if (channel >= TC_NUMBER_OF_CHANNELS)
00066 return TC_INVALID_ARGUMENT;
00067
00068
00069 tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
00070 bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
00071 bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
00072 bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
00073 bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
00074 bitfield->cpas << AVR32_TC_CPAS_OFFSET |
00075 bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
00076 bitfield->covfs << AVR32_TC_COVFS_OFFSET;
00077
00078
00079 if (global_interrupt_enabled) Disable_global_interrupt();
00080 tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
00081 (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
00082 (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
00083 (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
00084 (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
00085 (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
00086 (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
00087 (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
00088 tc->channel[channel].sr;
00089 if (global_interrupt_enabled) Enable_global_interrupt();
00090
00091 return 0;
00092 }
00093
00094
00095 int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)
00096 {
00097
00098 if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)
00099 return TC_INVALID_ARGUMENT;
00100
00101
00102 tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |
00103 (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));
00104
00105 return 0;
00106 }
00107
00108
00109 int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)
00110 {
00111
00112 if (opt->channel >= TC_NUMBER_OF_CHANNELS)
00113 return TC_INVALID_ARGUMENT;
00114
00115
00116 tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |
00117 opt->ldra << AVR32_TC_LDRA_OFFSET |
00118 0 << AVR32_TC_WAVE_OFFSET |
00119 opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |
00120 opt->abetrg << AVR32_TC_ABETRG_OFFSET |
00121 opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|
00122 opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |
00123 opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |
00124 opt->burst << AVR32_TC_BURST_OFFSET |
00125 opt->clki << AVR32_TC_CLKI_OFFSET |
00126 opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
00127
00128 return 0;
00129 }
00130
00131
00132 int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)
00133 {
00134
00135 if (opt->channel >= TC_NUMBER_OF_CHANNELS)
00136 return TC_INVALID_ARGUMENT;
00137
00138
00139 tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |
00140 opt->beevt << AVR32_TC_BEEVT_OFFSET |
00141 opt->bcpc << AVR32_TC_BCPC_OFFSET |
00142 opt->bcpb << AVR32_TC_BCPB_OFFSET |
00143 opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |
00144 opt->aeevt << AVR32_TC_AEEVT_OFFSET |
00145 opt->acpc << AVR32_TC_ACPC_OFFSET |
00146 opt->acpa << AVR32_TC_ACPA_OFFSET |
00147 1 << AVR32_TC_WAVE_OFFSET |
00148 opt->wavsel << AVR32_TC_WAVSEL_OFFSET |
00149 opt->enetrg << AVR32_TC_ENETRG_OFFSET |
00150 opt->eevt << AVR32_TC_EEVT_OFFSET |
00151 opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |
00152 opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |
00153 opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |
00154 opt->burst << AVR32_TC_BURST_OFFSET |
00155 opt->clki << AVR32_TC_CLKI_OFFSET |
00156 opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
00157
00158 return 0;
00159 }
00160
00161
00162 int tc_start(volatile avr32_tc_t *tc, unsigned int channel)
00163 {
00164
00165 if (channel >= TC_NUMBER_OF_CHANNELS)
00166 return TC_INVALID_ARGUMENT;
00167
00168
00169 tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;
00170
00171 return 0;
00172 }
00173
00174
00175 int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)
00176 {
00177
00178 if (channel >= TC_NUMBER_OF_CHANNELS)
00179 return TC_INVALID_ARGUMENT;
00180
00181
00182 tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;
00183
00184 return 0;
00185 }
00186
00187
00188 int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)
00189 {
00190
00191 if (channel >= TC_NUMBER_OF_CHANNELS)
00192 return TC_INVALID_ARGUMENT;
00193
00194
00195 tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;
00196
00197 return 0;
00198 }
00199
00200
00201 void tc_sync_trigger(volatile avr32_tc_t *tc)
00202 {
00203
00204 tc->bcr = AVR32_TC_BCR_SYNC_MASK;
00205 }
00206
00207
00208 void tc_sync_start(volatile avr32_tc_t *tc)
00209 {
00210 unsigned int i;
00211
00212 for(i=0; i<TC_NUMBER_OF_CHANNELS;i++)
00213 tc->channel[i].ccr = AVR32_TC_CLKEN_MASK;
00214
00215
00216 tc->bcr = AVR32_TC_BCR_SYNC_MASK;
00217 }
00218
00219
00220 int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)
00221 {
00222
00223 if (channel >= TC_NUMBER_OF_CHANNELS)
00224 return TC_INVALID_ARGUMENT;
00225
00226 return tc->channel[channel].sr;
00227 }
00228
00229
00230 int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)
00231 {
00232
00233 if (channel >= TC_NUMBER_OF_CHANNELS)
00234 return TC_INVALID_ARGUMENT;
00235
00236 return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);
00237 }
00238
00239
00240 int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)
00241 {
00242
00243 if (channel >= TC_NUMBER_OF_CHANNELS)
00244 return TC_INVALID_ARGUMENT;
00245
00246 return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);
00247 }
00248
00249
00250 int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)
00251 {
00252
00253 if (channel >= TC_NUMBER_OF_CHANNELS)
00254 return TC_INVALID_ARGUMENT;
00255
00256 return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);
00257 }
00258
00259
00260 int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)
00261 {
00262
00263 if (channel >= TC_NUMBER_OF_CHANNELS)
00264 return TC_INVALID_ARGUMENT;
00265
00266 return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);
00267 }
00268
00269
00270 int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
00271 {
00272
00273 if (channel >= TC_NUMBER_OF_CHANNELS)
00274 return TC_INVALID_ARGUMENT;
00275
00276
00277 if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
00278 Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);
00279
00280 return value;
00281 }
00282
00283
00284 int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
00285 {
00286
00287 if (channel >= TC_NUMBER_OF_CHANNELS)
00288 return TC_INVALID_ARGUMENT;
00289
00290
00291 if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
00292 Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);
00293
00294 return value;
00295 }
00296
00297
00298 int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
00299 {
00300
00301 if (channel >= TC_NUMBER_OF_CHANNELS)
00302 return TC_INVALID_ARGUMENT;
00303
00304
00305 if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
00306 Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);
00307
00308 return value;
00309 }