Re: [pci] PCI Master & Target access

["Sangmoon Kim" <dogoil@etinsys.com>]

Hi,
I've solved the problem that I asked with a little change on PCI core.
On /rtl/verilog/pci_wb_slave.v I found the code below.

wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I && pciw_fifo_empty_in && ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ;

The wdel_completion_allow variable is used for determining wheather the core end the transaction with ACK or RTY.

I changed the code like below because I didn't think the dependency between pciw_fifo's emptyness and  wb_slave's ACK is needed.

wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I &&  ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ;

Until now the code runs well.

Regards,
Sangmoon Kim

----- Original Message ----- 
From: Sangmoon Kim 
To: pci@opencores.org 
Sent: Saturday, August 09, 2003 1:16 PM
Subject: [pci] PCI Master & Target access


Hi,
I'm developing a PCI-VME bridge using the opencoreas' PCI core.
I get some data errors if other VME master accesses VME bus (wb_master) while PCI side (wb_slave) accesses VME bus.

Does any one had the problem?

Thank you in advance.

Regards,
Sangmoon Kim

--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml