[pci] Icarus Verilog vs. pci core.

[Stephen Williams <steve@icarus.com>]

I've fixed a few minor bugs in Icarus Verilog that were preventing
the pci core test bench from running. The current anonymous CVS
has these fixes. I've also fixed a questionable in:

    bench/verilog/wb_bus_mon.v (Patch at the end of this message)

I compile with this command file for Icarus Verilog:


    +incdir+$(PCI)/bench/verilog
    +incdir+$(PCI)/rtl/verilog

    +libdir-nocase+$(PCI)/bench/verilog
    +libdir-nocase+$(PCI)/rtl/verilog
    +libdir+$(XILINX)/verilog/src/unisims

    $(PCI)/bench/verilog/system.v

It runs for a while, but at the end of the regression test I
get the following error and $stop. Is this expected, or am I
going to need to start debugging this?

  test master 2 - Starting Memory Read, at           3570435000
  test master 1 - Starting Memory Read Line Multiple, at 
3570705000
  test master 1 - Starting Memory Read Line Multiple, at 
3571275000
  test master 2 - Starting Memory Read, at           3571935000
Signaled Target Abort bit not set in PCI Device Status register after 
read terminated with Target Abort
** VVP Stop(0) **
** Current simulation time is 3572045000 ticks.
 >

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

--- wb_bus_mon.v.orig   2002-08-13 04:03:51.000000000 -0700
+++ wb_bus_mon.v        2003-08-01 16:42:59.000000000 -0700
@@ -320,8 +320,10 @@ end // CAB_O monitor

  // address monitor for consecutive address bursts
  reg [`WB_ADDR_WIDTH:0] address ;
+reg [31:0]            ADDR_O_tmp;
  always@(posedge CLK_I or posedge RST_I)
-begin
+  begin
+     ADDR_O_tmp = ADDR_O + `WB_SEL_WIDTH;
      if (~CYC_O || ~CAB_O || RST_I)
          address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
      else
@@ -329,7 +331,7 @@ begin
          if (STB_O && ACK_I)
          begin
              if (address[`WB_ADDR_WIDTH] == 1'b0)
-                address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
+                address <= {1'b1, ADDR_O_tmp} ;
              else
              begin
                  if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
@@ -338,7 +340,7 @@ begin
                      $fdisplay(log_file_desc, "Consecutive address 
burst address incrementing incorrect") ;
                  end
                  else
-                    address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
+                    address <= {1'b1, ADDR_O_tmp} ;
              end
          end
      end

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