Re: [fpu] Add/Sub Unit Test Vectors

["Rudolf Usselmann" <rudi@inet.co.th>]

> From: Jamil Khatib <jamilkhatib75@yahoo.com> 
> Subject: Re: [fpu] Add/Sub Unit Test Vectors 
> 
> --- Rudolf Usselmann <rudi@inet.co.th> wrote:
> 
> > The INF and NAN are OUTPUTS. They are asserted when
> > one of the input
> > operands was a NAN or INF. Currently I don not
> > enforce that a INF or NAN
> > values is correctly represented on the sum output.
> > Should I add this ?
> > I thought it will be mostly used to generate an
> > exception ....
> 
> As far as I know that these special values must appear
> on FPU registers and not signals or exceptions only.

OK, I'll add that to the cores ...

> 
> But as I know from the IEEE std the denormalized
> numbers are so important in some calculations. I am
> not sure why but I'll give you examples tomorrow. but
> it should be supported for both inputs and outputs

I can't see why. Denormalized numbers are equivalent to simple
32 bit integers (except that they are only 23 bits).

> >
> > > 4. How do you handel NAN and INF numbers at the
> > input?
> >
> > Assert INF and/or NAN output signal.
> 
> 
> Note: denormalized numbers aer no. that have  exp=0
> and fract!=0

Yes, I know that.

> I think the issues of normalizations, special values
> and exceptions should be handeled globally or the
> cores will generate and use different values and that
> will reflect incorrect no. on the registers.

Normalization can not be handled globally. The FASU has to normalize
a 25 bit sum, the FMUL unit, has to normalize a 48 bit product.

Exceptions, on the other hand, must be handled by some sort of
exception handler ...

> what I am not sure about it is should we have an
> instruction to normalize denormalized numbers??

Yes, ALMOST ! What we need is Integer to Floating Point and
vise versa conversions.

> I am going to write a summary of what I know of IEEE
> std.

I think we all have a copy of that, but thanks anyway ...

> Regards
> Jamil Khatib

rudi