Re: [fpu] Add/Sub Unit Test Vectors

["Rudolf Usselmann" <rudi@inet.co.th>]

Sorry, haven't seen your post - I need to add myself to the mailing list !

Anyway, here are your answers and an attached pdf file. Please keep in mind
that this is work in progress (active progress that is ;*).

> Hi,
> 
> Could you please write some desicription about the
> core and its interface so as to create compatible code
> in  VHDL.
>
> we should also define the specifications of the FPU
> blocks interfaces

I think Damjan already commented on this ...

> As I see the interface has:
> 1. signals for INF and NaN but teh core does not
> encode them to the output, So do you suggest to
> generate these special values in a seperate block.

The INF and NAN are OUTPUTS. They are asserted when one of the input
operands was a NAN or INF. Currently I don not enforce that a INF or NAN
values is correctly represented on the sum output. Should I add this ?
I thought it will be mostly used to generate an exception ....

> 2. Denormailized numbers are used as outputs so an
> external block will do the normalization??

Please explain how you came to that conclusion ?!

I thought I designed it so that the output IS normalized ?!
Meaning the leading 1 is hidden and the exponent is adjusted ...

As far as I know, the output is normalized - unless you found a bug ...

> 3. Do your core accept denormalized numbers? it should
> do.

It has been designed to work with Normalized numbers. I'm not sure what
it will actually do if a denormalized number is presented.

> 4. How do you handel NAN and INF numbers at the input?

Assert INF and/or NAN output signal.

> Regards
> Jamil KHatib

Cheers,
rudi

fasu.pdf