Re: [fpu] Add/Sub Unit Test Vectors

["Damjan Lampret" <damjan.lampret@arnes.si>]

----- Original Message -----
From: Jamil Khatib <jamilkhatib75@yahoo.com>
To: <fpu@opencores.org>
Sent: Tuesday, July 11, 2000 3:19 PM
Subject: Re: [fpu] Add/Sub Unit Test Vectors


> Hi,
>
> Could you please write some desicription about the
> core and its interface so as to create compatible code
> in  VHDL.

Actually Rudi wrote HTML page and it is in CVS. But since you were the last
one making changes on FPU web pages we decided to wait for you and decide
together whether fasu is a separate project/core or it should become part of
the "FPU" project. In the mean time Rudi and I have already agreed what we
should do to develop FPU. And I was just about to publish this news on this
mailing list. Basically Rudi is working on implementation of FPU and I need
to develop 'C' program for generating test vectors. At the moment we have
decided to optimize for std cell ASIC 0.18/0.25u and not for FPGAs.

I guess it would be good to write some sort of specs (anybody interested?).
Also Jamil you asked some good question that deserve answers (I'll am away
for day or two so I can't answer them right now; I hope others will engage
into discussion).

regards,
Damjan