[ethmac] Ethernet core on FPGA - WISHBONELESS INTERFACE!

[simos@csd.uoc.gr]

Hello everybody and congratulations on the feedback sofar!

I want to write an Ethernet core to be used in future designs, but 
without having to use wishbone interface on the host interface part of 
the design.

As I can see, the ethernet core communicates with the host only by 
using DMA transfers. Additionally, wishbone interface has to be used 
throughout the design.

Has anybody used the ethernet core on an FPGA but with another host 
interface (lets say a small memory and a loopback part)?

I am using MaxPlus and Quartus and implement the designs on a 
FLEX10K100 FPGA.

Thanx in advance! Looking forward 2 hearing from u ASAP!

Mimis Simos.
--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml