RE: [ethmac] RMII, SMII

["Igor Mohor" <igorm@opencores.org>]

Hi, Chang,

Fixed. Thanks.

Best regards,
	Igor

> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of C.T.Lin
> Sent: 8. marec 2002 6:16
> To: ethmac@opencores.org
> Subject: RE: [ethmac] RMII, SMII
>
>
> Hi,
>   I find a small bug in eth_wishbone.v in treating bigendian
>
> // Tx data selection (latching)
> always @ (posedge MTxClk or posedge Reset)
> begin
>   if(Reset)
>     TxData <=#Tp 8\'h0;
>   else
>   if(TxStartFrm_sync2 & ~TxStartFrm)
> //    TxData <=#Tp TxData_wb[7:0];
>     TxData <=#Tp TxData_wb[31:24];				//
> Big Endian Byte Ordering
>   else
>   if(TxUsedData & Flop)
>     begin
>       case(TxByteCnt)
> //        0 : TxData <=#Tp TxDataLatched[7:0];
> //        1 : TxData <=#Tp TxDataLatched[15:8];
> //        2 : TxData <=#Tp TxDataLatched[23:16];
> //        3 : TxData <=#Tp TxDataLatched[31:24];
>         0 : TxData <=#Tp TxDataLatched[31:24];      // Big Endian
> Byte Ordering
>         1 : TxData <=#Tp TxDataLatched[23:16];
>         2 : TxData <=#Tp TxDataLatched[15:8];
>         3 : TxData <=#Tp TxDataLatched[7:0];
>       endcase
>     end
> end
>
>   Best regard!
>                            Chang-Tsun Lin
>
>
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