In some devices(phy),signals are outputed on the falling edge of the reference clock to meet the 10 ns
setup and hold time. Is that necessary?
In this core,signals(txd,txen) are outputed on the rising edge of tx_clk.
Both ways are ok?
Regards.
& nbsp; yxzhou
"Igor Mohor" <igorm@opencores.org>
发件人： owner-ethmac@opencores.org2001-12-24 18:01
请答复 给 ethmac
&nb sp; 收件人： <ethmac@opencores.org>
抄送：
主题： RE: [ethmac] mii rx hold time
No, tx_clk and rx_clk are not synchronous. PHY generates both signals. Yes, the hold time will meet. tx_clk and rx_clk
are 25 Mhz (40 ns).
Regards,
Igor
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@ope ncores.org]On Behalf Of zou.yixin@zte.com.cn
Sent: 24. december 2001 9:38
To: ethmac@opencores.org
Subject: [ethmac] mii rx hold time
hi,
Merry Christmas!
The following is quoted from 802.3-2000E.
"Figure 22–15 shows the timing relationship for the signals associated with the receive data path at the MII
connector. The timing is referenced to the rising edge of the RX_C LK. The input setup time shall be a minimum
of 10 ns and the input hold time shall be a minimum of 10 ns."
"Figure 22–14 shows the timing relationship for the signals associated with the transmit data path at the MII
connector. The clock to output delay shall be a minimum of 0 ns and a maximum of 25 ns."
When i send data synchronouly with respect to TX_CLK rising edge,can the 10ns hold time met ?I assume the tx_clk and rx_clk are synchronous(right?). How t o avoid the hold time violation.
Thanks.
yxzhou.