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RE: [ethmac] Testing ethernet core
hi'
i'm using modelsim, and i have same problem too.
> I'm looking at the 'core' (Tx, Rx, Control, Status, MIIM) in modelsim at the moment. will provide feedback.
>
> Igor, I'm finding that some compilers don't have a binding order for '~' and '&' so they don't know which order to process - I think you assume '~' will be taken to bind closer so that (eg)
>
> assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
> you mean: TxCarrierSense = (~r_FullD) & CarrierSense_Tx2;
>
> -correct, or not? (maybe the order is part of standard verilog but some compilers do not comply? I don't know...)
>
> thanks, Dan.
>
> ----- Original Message -----
> From: jimkje at adaptivemicro dot com
> To: ethmac at opencores dot org, ethmac at opencores dot
> org
> Date: Thu, 9 Aug 2001 08:29:45 -0500
> Subject: RE: [ethmac] Testing ethernet core
>
> > Igor,
> >
> > I'll be focusing on compiling this core into two
> > different FPGA's. The
> > Altera 1K100 and also 20K400E devices. I'll also be
> > attempting to
> > "leave-out" the transmit path for one configuration, in
> > order to save logic
> > elements.
> >
> > I will need to do some functional verification at the top
> > level. I'll be
> > happy to share my results.
> >
> > Jim
> >
> >
> > -----Original Message-----
> > From: Igor Mohor (uni-mb) [<A
> > href="/cgi-bin/post.cgi?cmd=new&to=igor%20dot%20mohor%20at%20uni-mb%20dot%20si&msg=/ml-archive/ethmac/msg00023.shtml">mailto:<font
> > class=email>igor dot mohor at uni-mb dot si</font>]
> > Sent: Wednesday, August 08, 2001 3:17 AM
> > To: Ethmac@Opencores. Org
> > Subject: [ethmac] Testing ethernet core
> >
> >
> > Hi, guys, girls,
> >
> > I noticed that several of you are trying to use or test
> > ethernet core.
> > I would like to suggest to spread the work. There are
> > several things to be
> > written (i.e. ethernet phy. model, address recognition
> > system, testing
> > suite,
> > etc.).
> >
> > I don't want that everybody spend too much time in
> > testing the same things.
> >
> > So I would like to ask each of you which parts are you
> > willing to test in
> > details.
> > Please share that information and work with others.
> > That's the fastest way
> > to achieve
> > our goal: a fully operational ethernet MAC in FPGA and
> > ASIC.
> >
> > I get several questions for help every day and I have to
> > say that it is a
> > real pleasure
> > to answer because I know that all my work (and nights)
> > spent on the project
> > are starting
> > to bring results.
> >
> > Regards,
> > Igor
> >
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