RE: [ethmac] Testing ethernet core

[Jim Kjendalen <jimkje@adaptivemicro.com>]

Igor,

I'll be focusing on compiling this core into two different FPGA's.  The
Altera 1K100 and also 20K400E devices.  I'll also be attempting to
"leave-out" the transmit path for one configuration, in order to save logic
elements.

I will need to do some functional verification at the top level.  I'll be
happy to share my results.  

Jim


-----Original Message-----
From: Igor Mohor (uni-mb) [mailto:igor.mohor@uni-mb.si]
Sent: Wednesday, August 08, 2001 3:17 AM
To: Ethmac@Opencores. Org
Subject: [ethmac] Testing ethernet core


Hi, guys, girls,

I noticed that several of you are trying to use or test ethernet core.
I would like to suggest to spread the work. There are several things to be
written (i.e. ethernet phy. model, address recognition system, testing
suite,
etc.).

I don't want that everybody spend too much time in testing the same things.

So I would like to ask each of you which parts are you willing to test in
details.
Please share that information and work with others. That's the fastest way
to achieve
our goal: a fully operational ethernet MAC in FPGA and ASIC.

I get several questions for help every day and I have to say that it is a
real pleasure
to answer because I know that all my work (and nights) spent on the project
are starting
to bring results.

Regards,
	Igor

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