RE: [ethmac] Signed - unsigned problems

["Illan Glasner" <iglasner@zumanetworks.com>]

8-Aug-01

   Igor Hi,

         Do you use verilog or VHDL ?

in verilog there is no specail distinguish between signed and unsigned.
I used many times ffff.. etc and never had a problem.

what tool do you use ? mine is verilog XL or NC from Cadance.

As for idea well you can try 33 bit FF and ignore the bit 33 but I
hardly think this is the solution as most likely the problem is
somewhere else and not this sign/unsign.

for example you might want to verify you didn't define by mistake crc
reg to be [30:0] instead of [31:0] which will result in 7fff_ffff ?

BTW a "easier way I belive to avoid counting the "f" is simple write
{32{1'b1}} or if you really like the "f" than {8{4'hf}} this way no need
to count and see there is a missing or not missing number. or if you
feel you like this long "f" tail than maybe use _ to make it more clear
like 32'hffff_ffff.

have a nice day

   Illan
   


-----Original Message-----
From: Igor Mohor (uni-mb) [mailto:igor.mohor@uni-mb.si]
Sent: Monday, August 06, 2001 5:22 AM
To: Cores@Opencores. Org; Ethmac@Opencores. Org
Subject: [ethmac] Signed - unsigned problems


Hi, guys and girls,

Looks like compilers by default understand 32-bit numbers differently.

Here is a description of such a problem:

I'm having problems with 32 bit numbers; My compiler seems to be
assuming 
that code like:
    Crc <= #1 32'hffffffff; (in crc.v)
refers to a SIGNED number and so won't accept a hex string larger than 
7FFFFFFF - I assume that your code treats the register(?) unsigned.

any ideas how to get round this one?



Regards,
	Igor
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