[ethmac] A question

[zixim <zixim@chinaren.com>]

Hi,

In this design, all data vary at the positive edge of clock.
But, I think, there  be some time for the data to be
valid, that is, data should have a setup time.

So I think that things will be better if the data vary at the 
negative edge of clock signal. There will be half cycle time 
for the data to setup.

But I'm not very sure. Please tell me your thought. thanks!

xiaomao
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