Re: [ethmac] Ethernet MAC 10/100 Mbps

[nbase <nbase@nbase.com>]

24-May-00

   Hi,

         There are few correction I belive you need to do in the state
diagram, as well as something you omite (or did I missed sonething)

It look like both diagram show data from host to MII while the receive I
belive should be the other way arround.

You might consider support RMII as pin count become more and more an issue
and there is no more problem getting phy with rmii support or even only rmii.

What is tx_err for ? (rx_err is needed as the py might send you if
appropriate error occur).

Do you expect that the recive will work with rx_clk and transmite with
tx_clk and both will be connected to the host with two different clock
domain ? I belive a better solotion will be to put a small fifo in the
receive path and have the rx as well as tx work in tx_clk this way the
interface to your host will be syncronus to one clock domain.

I don't see any signal going between the tx and rx , for example flow control

Where do you do the partition check ?

What is this Jam Generator ? do you plan to send certain pattern ? jam can
be what ever you like.

What about sending flow control packet for full duplax mode ?

I also suggets to give to each line in the drawing signal of name that
explain what it does as some arrow you seem to ommite the description like
in the "SFD Detector" etc.

What is the "Address Rec" suppose to do ?

well I guess this already become a long Email so I will stop now

have a nice day

   

At 02:52 PM 05/23/2000 +0700, you wrote:
>
>Hi, welcome
>
>We are doing behavioral design with Verilog HDL for the MAC (the diagrams
>are in ethmac web page). But me and Novan have final exams until end of
>May, we really can't do any significant progress until the exams finished.
>We hope pin descriptions will be available soon and we can show you
>the behavioral design in the middle of June.
>
>regards, 
>
>Mahmud 
>
>On Mon, 22 May 2000, Rotem Gazit wrote:
>
>> Hi,
>> 
>> This project seems very interesting.
>> 
>> Pls. send more information on current project status and the kind of help
>> you need.
>> 
>> Regards,
>> Rotem.
>> 
>>
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>> Rotem Gazit   
>> System & Architecture Department 
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>>
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>
>