Re: [ecc] My Viterbi Project and Problem(help)

[Lior Shtram <liors@flextronics.co.il>]

Hi Peter,

It seems your answer is within your question - you don't have to use 
register exchange - you can use traceback. That can save you realy a lot 
of size by using block memories - though implementation will be a little 
bit more complex. question - f(max) is your implementation result or a 
requirement?

regards,
Lior

> >
> >
> > Hi ,
> > I am a student. I have finished my viterbi
> > project:K=7;Rate=1/2,2/3,7/8;3 bit Soft ;f(max)=11MHz. but it is
> > too
> > large (6464 Logic element in Altera's FPGA). I use Register
> > Exchange
> > methde to implement Survivor Select and Update. So I used 64 ACS
> > Unit.
> >
> > How can I do better in the decreasing area of the viterbi decoder
> > or
> > what is the problem of my decoder?
> >
> >
> > Thanks!
> >
> > Peter Ma
> >
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