Re: [ecc] My Viterbi Project and Problem(help)

[Nanda <nanda@cdotb.ernet.in>]

HI , did u try the trace back method  ? and by the way, while tracing back
did u start with any arbitrary state or did u find the state with the
smallest metric and start with that state to trace back ?
bye , cheers

 On Sat, 1 Dec 2001 malitj@263.net wrote:

> Hi ,
> I am a student. I have finished my viterbi 
> project:K=7;Rate=1/2,2/3,7/8;3 bit Soft ;f(max)=11MHz. but it is too 
> large (6464 Logic element in Altera's FPGA). I use Register Exchange 
> methde to implement Survivor Select and Update. So I used 64 ACS Unit.
> 
> How can I do better in the decreasing area of the viterbi decoder or 
> what is the problem of my decoder?
> 
> 
> Thanks!
> 
> Peter Ma
> 
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K.G.Nanda Kumar
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Satellite Communication
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