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[cvs-checkins] pci/rtl/verilog pci_master32_sm_if.v

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	03/06/12 09:13:02

Modified files:
	rtl/verilog    : pci_master32_sm_if.v 

Log message:
	Changed one critical PCI bus signal logic.

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