[cvs-checkins] pci/apps/test bench/verilog/test_bench.v bench ...

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	03/06/12 01:56:12

Added files:
	apps/test/bench/verilog: test_bench.v test_bench.v.bak 
	                         test_bench.v~ timescale.v 
	                         timescale.v.bak 
	apps/test/rtl/verilog: cds.lib hdl.var ncelab.args ncprep.log 
	                       ncsim.args ncvlog.args pci_bridge32.v 
	                       pci_test_top.v.bak pci_test_top.v~ 
	                       pci_test_top_1clk.v pci_test_top_1clk.v~ 
	                       pci_test_top_2clks.v 
	                       pci_test_top_2clks.v.bak 
	                       pci_test_top_2clks.v~ 
	                       pci_user_constants.v 
	                       pci_user_constants.v.bak 
	                       pci_user_constants.v~ test.v test.v.bak 
	                       test.v~ 
	apps/test/sim/rtl_sim/run: cds.lib clean debug.do hdl.var nc.scr 
	                           nc.scr~ ncelab.args ncprep.log 
	                           ncsim.args ncsim.key ncsim.tcl 
	                           ncvlog.args run_sim.scr run_sim.scr~ 
	                           test.cr.mti test.mpf vsim.wlf 
	apps/test/syn/synplify: pci_test_top.cel pci_test_top.prd 
	                        pci_test_top.prj pci_test_top.prj~ 
	                        pci_test_top.sdc.bak pci_test_top.sdc~ 
	                        pci_test_top.sfp pci_test_top.ucf 
	                        pci_test_top.ucf.bak 
	                        pci_test_top_1clk.sdc 
	                        pci_test_top_1clk.sdc~ 
	                        pci_test_top_2clks.sdc 
	                        pci_test_top_2clks.sdc~ stdout.log 

Log message:
	Added a test application!

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