[cvs-checkins] mem_if/ ench/verilog/adv_bb.v ench/verilog/mem ...

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_if
Changes by:	mihad	03/06/05 15:47:04

Modified files:
	bench/verilog  : adv_bb.v mem_if_bench.v mem_if_bench_defines.v 
	                 timescale.v wb_model_defines.v 
	rtl/verilog    : mem_if_flash_if.v mem_if_sdram_defines.v 
	                 mem_if_sdram_dp.v mem_if_sdram_flash_defines.v 
	                 mem_if_sdramcnt.v mem_if_top.v 
	sim/rtl_sim/run: debug.do 

Log message:
	Added 16 bit data bus width support!

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