[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] camera/rtl/verilog camera_cb_table.v camera_cr ...

CVSROOT:	/home/oc/cvs
Module name:	camera
Changes by:	simons	03/06/03 16:39:02

Modified files:
	rtl/verilog    : camera_cb_table.v camera_cr_table.v 
	                 camera_top.v camera_wb_if.v camera_y_table.v 

Log message:
	Slave WB address bus width changed to 8 bit.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml