[cvs-checkins] uart16550/rtl/verilog uart_regs.v uart_transmi ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/10/29 18:00:55

Modified files:
	rtl/verilog    : uart_regs.v uart_transmitter.v 

Log message:
	fixed parity sending and tx_fifo resets over- and underrun

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