[cvs-checkins] dbg_interface/rtl/verilog dbg_trace.v dbg_top. ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	dbg_interface
Changes by:	mohor	01/10/19 13:40:02

Modified files:
	rtl/verilog    : dbg_trace.v dbg_top.v dbg_sync_clk1_clk2.v 
	                 dbg_registers.v dbg_register.v dbg_crc8_d1.v 
Added files:
	rtl/verilog    : timescale.v 
Removed files:
	rtl/verilog    : dbg_timescale.v 

Log message:
	dbg_timescale.v changed to timescale.v This is done for the simulation of
	few different cores in a single project.

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